1. Field of the Invention
The invention relates generally to semiconductor memory devices. Particularly, the invention relates to Electrically Erasable Programmable Read-Only Memory (E.sup.2 PROM) or Electrically Alterable Read-Only Memory (EAROM) and to Non-Volatile Random Access Memory (NVRAM).
2. Prior Art
The use of E.sup.2 PROM as a semiconductor memory device is well known in the prior art. In such devices charge stored on a floating gate of an FET of each memory cell is used to represent a logical "0" or a logical "1". When a particular memory cell is addressed, the state of the charge on the floating gate determines whether or not the channels of the FET of which the floating gate forms a part is conductive and hence the amount of current which flows through the selected cell.
The prior art describes several methods for transferring charge to and from the floating gate. Charging of the floating gate is often referred to as "programming" and the transfer of charge from or discharging the floating gate is referred to as "erasing." In an article entitled, "An Electrically Alterable ROM and It Doesn't Use Nitride," by J. W. Kelley et al (Electronics, Dec. 9, 1976, p. 101 et seq), avalanche electron ejection is used to program a Read Only Memory (ROM) and avalanche hole injection is used to erase the ROM. In another article entitled "Electrically Alterable 8192 Bit N-Channel MOS PROM," by R. G. Miller et al (JSSCC Proceedings, February 1977, p. 188 et seq), a "hot" electron injection method is used for programming and the so-called Fowler-Nordheim emission technique is used for erasing. U.S. Pat. No. 4,099,196, Ser. No. 810,912, filed June 29, 1977, issued July 4, 1978 to Simko, teaches a memory cell utilizing both oxide conduction for both programming and erasing. Other memory devices which use "hot" electron injection for programming and oxide conduction (tunneling) for erasing are described in U.S. Pat. No. 4,119,995, Ser. No. 778,574, filed Mar. 17, 1977, issued Oct. 10, 1978 to Simko, and an article entitled, "An Electrically Alterable Nonvolatile Memory Cell Using a Floating Gate Structure," (IEEE JSSC, April 1979, p. 498 et seq).
Although the above techniques work well for their intended purposes, they suffer from a common drawback. In all cases the techniques require relatively large power consumption, high field conductive path and long times for programming and erasing.
The prior art attempts to solve the aforementioned problems by conducting charge through an oxide structure in order to charge and/or discharge the floating gate. U.S. Pat. No. 4,203,158 (Ser. No. 969,819, filed Dec. 15, 1978, issued May 13, 1980) to DiMaria et al is an example of such structures. In the patent a graded layer of silicon rich silicon dioxide in conjunction with a thermal silicon dioxide between a silicon substrate and a metal electrode is used to conduct the charge. This structure is commonly referred to as a Single Electron Injection Structure (SEIS) because of its ability to lower the electric field for injection of electrons for one polarity of applied field. U.S. Pat. No. 4,099,196 (Ser. No. 810,912, filed June 29, 1977, issued July 4, 1978) to Simko describes a triple layer polysilicon cell for use in an E.sup.2 PROM. Silicon dioxide (SiO2) is used as the conductive path to the floating gate. The SiO2 is thermally grown from a rough surfaced, lightly doped polysilicon gate electrode.
In yet another improvement, the prior art uses a Dual Electron Injection Structure (DEIS) as the medium for transferring electrons to and from the floating gate. The DEIS material is a composite of three layers of silicon dioxide which has been chemically vapor deposited so that the lower and upper layers have excess silicon atoms which when placed adjacent to lower and upper conductive electrodes of polysilicon causes a conduction of electron through the middle silicon dioxide layer at a reduced electric field. The middle layer prevents tunneling of charge at a lower electric field preventing the loss of charge from the floating gate in the nonvolatile memory cell.
A nonvolatile memory cell including a DEIS structure is disclosed in an article entitled "Dual Electron Injector-Structure Electrically Alterable Read-Only Memory Model Studies," DiMaria et al (IEEE Transactions on Electronic Devices, Vol. ED-28, No. 9, September 1981) and copending patent application Ser. No. 124,003, filed February 26, 1980, and assigned to the assignee of the present invention. The memory device uses a cell structure composed of an n-channel MOS transistor with a DEIS structure positioned between a control gate and a "floating" polycrystalline silicon gate. A negative voltage is applied to the control gate to effectuate writing of the cell. This negative voltage causes the injection of electrons from the top silicon rich SiO2 injector layer of the DEIS structure to the floating polysilicon layer. Likewise, the cell is erased by applying a positive voltage to the control gate. The gate ejects electrons from a bottom silicon-rich (SiO2) injector layer of the DEIS material to the floating polysilicon layer.
Other examples of memory cells using a DEIS material or the like to transfer charge to and from a floating gate FET are disclosed in U.S. patent applications Ser. Nos. 192,579 filed Sept. 30, 1980; 192,580 filed Sept. 30, 1980; and 219,285 filed Dec. 22, 1980.
Because of the effectiveness with which the DEIS material transfers charges to and from a floating gate, it is desirable to incorporate it in a multiple layer polysilicon storage structure. However, the DEIS rapidly oxidizes to silicon dioxide during a typical oxidation step. Once the DEIS oxidizes it loses its effectiveness. Due to the lack of a suitable process which prevents the DEIS from oxidizing, the prior art has failed to capitalize on its use in a multiple poly process.